Improve LED manufacturing via in-line monitoring and SPC (MAGAZINE)

July 30, 2013
In-line monitoring of defects on LED wafers allows manufacturers to understand which defects impact yield and to apply that information in a constant effort to improve yield, explains Steven Chen.

This article was published in the July/August 2013 issue of LEDs Magazine.

View the Table of Contents and download the PDF file of the complete July/August 2013 issue, or view the E-zine version in your browser.


LED manufacturing is undergoing a tremendous transformation. The evolution to high-brightness LEDs, larger wafer size, and new complex architectures make LED manufacturing more challenging than ever before. Even though these trends greatly benefit the advancement of the solid-state lighting (SSL) industry in terms of LED efficiency and performance, they can potentially impact yield in a negative way. In order for LED manufacturers to stay competitive in this dynamic environment, they need to have a comprehensive in-line process control strategy to improve the yield and drive down the cost of LEDs and SSL end products.

Currently, most LED manufacturers rely on inspection tools to analyze wafers and document defects of interest (DOI). Defect density is typically utilized as the gauge for statistical process control (SPC). However, the drawback of this approach is the fact that there can potentially be a lot of nuisance defects that do not cause yield loss. In looking at a defective wafer through an inspection tool, how do you determine which defects are killer defects that impact the yield or electrical performance, and which defects are simply a nuisance? Manufacturers need to detect killer defects at the earliest possible time in terms of the repetitive epitaxial-growth wafer-production runs in an MOCVD (metal organic chemical vapor deposition) reactor. Ideally, the manufacturer will optimize the MOCVD process over time to reduce killer defects, whereas a line without such monitoring can lead to what's often called an excursion — or the shutdown and revamping of part of the manufacturing process.

FIG. 1

We know that in-line monitoring is critical in determining how defects affect the yield and a proper strategy would have tremendous return on investment (ROI). Further to the point, the current method of using total defect density is impractical. Hence, we will introduce a systematic methodology to identify yield-impacting defects and mapping the relationship of defects to yield.

LED manufacturing process

Before we jump into the details of the advanced process control technique, we want to take a step back and go over the LED manufacturing process flow. Understanding this process flow can help us to understand where crucial inspection points occur, and how process control can help improve time to corrective actions, which translates to higher ROI. A simplified version of the LED manufacturing process flow is depicted in Fig. 1 (above). In general, the manufacturing process consists of four essential stages — namely substrate, epitaxy, FEOL (front end of line), and BEOL (back end of line) — before going to final assembly.

First of all, the main substrate utilized in the production of LEDs is sapphire, gallium arsenide, or silicon carbide. There are also other initiatives for alternative substrates such as gallium nitride and silicon. With any substrate, a crystalline boule is produced in a similar fashion as the semiconductor process in the integrated circuit (IC) industry. The boule is normally sliced into very thin wafers with a diamond saw, and after slicing, they are polished via a rigorous process before being shipped to the LED manufacturer for further processing.

In the next stage known as epitaxy, additional layers of semiconductor crystal are grown on the surface of the wafer. MOCVD is a popular method for the epitaxial growth of p and n layers with quantum wells in between. The typical thickness of the p and n layers combined is around a few microns. It is important to have an inspection point before MOCVD because poor quality of the incoming substrate can potentially be the culprit of future electrical probe test failures downstream — such as failing forward voltage and reverse leakage current specifications.

Furthermore, defects from substrate and epitaxial processes can impact device performance, reliability, and yield. Equipment such as the Candela 8620 is capable of performing unpatterned wafer inspection at the substrate and epitaxy stages. It is crucial to catch defects at these early stages to allow faster time-to-root-cause determination and improved MOCVD reactor uptime and yield. In addition, the wafer inspection system is not only able to catch defects precisely, but it also classifies the defects accurately. This information is important for in-line process monitoring and SPC control.

Front-end processes

The next steps after epitaxial growth are the FEOL steps. FEOL in the LED process is similar to the semiconductor process but with fewer steps, and involves the wafers going through cleaning, lithography, etch, metallization, deposition, and anneal before going to BEOL. Patterning for enhancing light extraction also happens in the FEOL steps.

It is important to realize that, for any single set of wafers that goes through a production run, bad die bear the same cost as good die because bad die also have to be processed all the way through the LED manufacturing steps. Therefore, early defect detection and remediation when a line is started is the key to reducing manufacturing cost over time.

As LED structures become more complex, the ability to bin defects and understand the location of defects becomes increasingly important and requires inspection through the FEOL stages. The same defect on different LED structures will have different yield or electrical performance impact. In addition, defects with certain attributes are more critical and yield relevant than others at certain locations.

The inspection equipment's defect detection sensitivity and accurate classification capabilities are needed to ensure that manufacturers have a good set of data for analysis and process control. Wafer inspectors such as the WI-2280 are capable of inspecting all patterned wafers at various process steps such as lithography, etch, and metallization. In addition, the WI-2280 has a high defect capture rate, a unique defect classification capability, and an advanced recipe tuning engine that can be tightly integrated with advanced analysis software for process control and further evaluation.

Back-end processes

After the wafers go through FEOL, they go on to BEOL where die singulation, testing, and sorting take place before final assembly. Pre-dicing and post-dicing singulation inspection is essential to enable process control and improve the yield. Post-singulation should look for defects to ensure that the singulation tooling does not damage the wafers. For example, scratches on the die and the presence of foreign matter can potentially cause the die to crack during testing. The WI-2280 is also utilized for BEOL inspection to look for yield-relevant defects.

After die singulation, die attachment and wire bonding take place before encapsulation and final assembly. Packaged LED inspections to examine assembly defects such as missing die, defective wire bonding, and misplacements also happen at this stage before taping and shipping them out.

Finally, it is crucial to tie these inspections together and perform process control. The inspection equipment's defect detection sensitivity and classification capabilities need to be matched with yield management software that ties all the data together. The software needs to be capable of taking the inspected data from various inspection points and providing analysis and monitoring. In the next section, an example of in-line monitoring is introduced to demonstrate how to tie the data together to provide meaningful analysis and results.

Methodology overview

As mentioned before, it is crucial to distinguish yield-impacting defects from nuisance because not all defects impact the final yield. Thus, we need to understand the relationship between epitaxial defects and their impact on yield, as well as to create a systematic approach in separating yield-impacting DOI from nuisance. In order to establish a proper process control loop, advanced defect equipment such as that depicted in Fig. 1 is needed. Defect information inspected from substrate, epitaxy, FEOL, and BEOL can feed into an automated defect analysis tool. In the case presented here, we are going to focus on whether the epitaxial defect density correlates to yield.

FIG. 2

One approach to separate yield-impacting DOI from nuisance is to use what is called kill ratio analysis. Kill ratio represents a proportion of defects estimated to cause die failure. The kill ratio is derived from data gathered over prior production runs and is used to find the amount of defects on a current inspection that will cause die failure at the end of the process.

In order to understand how kill ratios help in separating yield-impacting DOI from nuisance, we need to understand the kill ratio model terminology. Fig. 2 (above) illustrates this concept. Bin data represents good or bad die identified by bin code. In addition, the defect data identifies clean or dirty die. A clean die contains no detected adder defects (such as particles), while a dirty die contains detected adder defects. The square boxes represent die and the dots represent defects. Green boxes indicate good die while white boxes indicate bad die. Therefore, good clean die means good die without defects. Good dirty die means good die that have defects. Furthermore, we also have total clean die and total dirty die.

The equations below are the yield and kill ratio formulas.

Generally, yield is simply the number of good die divided by the total number of die. In this case, however, we are focused on the yield impact strictly of the die that have at least one instance of the defect of interest, and that leads to the aforementioned formulas. In an actual production scenario, manufacturers would perform such an analysis on different types of defects. By binning defect attributes such as defect size and defect location with the kill ratio results, one will finally be able to observe the correlation to yield. In other words, defects with higher kill ratio have more negative impact on the yield.

After the data is gathered, we need to obtain accurate bin sort data, a list of wafers, yield information, and defect types from the inspection tools. Then, we use a yield management software tool, such as KLA-Tencor's Klarity LED, to perform the analysis. Here, we need to ensure that the defect map accurately aligns with the bin sort map. It is crucial to have an accurate wafer alignment because it is the basis of the kill ratio analysis. Using this kill ratio information, we can derive the yield-impacting DOI definition. Once we have obtained the DOI definition, we can apply it to all wafers. Upon finishing the kill ratio analysis, we can then identify yield-impacting defects by correlating the defect counts to the final bin yield. Finally, we can also obtain trend charts and be able to set upper control limits and SPC controls. The analysis is repeated until the yield-impacting DOI definition is satisfied.


Example and experimental results

Table 1 includes an example of a theoretical yield study and correlation results that illustrate this advanced defect identification methodology. In the example, assume that we are given 20 wafers with individual yield information and an average or baseline yield of 76%. Layer, class, size, wafer zone, in-die region, and signature membership are a few examples of defect attributes that can be analyzed. In this case, we take defect size as the attribute under study while Klarity LED was used to correlate yield-impacting defects with defect size.

In Fig. 3, we illustrate how to determine the yield-impacting defect attributes for four different theoretical defect types. Starting with a certain defect type, the defect count and the kill ratio with respect to its defect size are plotted. A dotted threshold line is drawn whenever sudden kill ratio jumps appear. In the case of defect type 1, defect size greater than three is the threshold where the kill ratio makes a significant jump. The same experiment goes for defect type 2, defect type 3, and defect type 4. Essentially, the defect size binning is based on the kill ratio threshold number. Potentially, one can have as many segments as one likes in order to see the impact of the yield with any defect size combination.

FIG. 3

After performing kill ratio analysis on all defect types, the final yield-impacting DOI definition is shown in Table 2. Bin 1 indicates a low-impacting DOI bin and bin 2 shows yield-impacting DOI bins that contain killer defects.

The next phase of the analysis is to apply the yield-impacting DOI definitions to each wafer analyzed. Ultimately, we need to sum up all yield-impacting defects and see how well they correlate with the final yield. Twenty wafers with their total number of yield-impacting defects and total defects are shown in Fig. 4.


You can see that the total defect counts do not correlate to yield well. For example, if one sets the upper control limit (UCL) at 1400 total defects, three wafers have defect counts greater than 1400. These are the wafers that contain the most defects; however, their yields are relatively high compared to the baseline average yield of 76.25%. Clearly, many of those defects do not translate to yield loss.

FIG. 4

On the other hand, if one sets the UCL to 1000 yield-impacting defects, again, three wafers have more defect counts than 1000. Interestingly, their yields are 16.25% lower than the baseline yield. As a result, one does not find wafers that have high yield-impacting defect counts with high yields. This further solidifies the methodology.

Fig. 5 depicts two correlation charts using these twenty wafers. The top graph compares yield versus total defect counts, and the bottom graph plots yield versus yield-impacting defect counts. The bottom graph makes more sense because it shows that as the yield-impacting defect counts increase, the yield decreases. SPC control on yield-impacting defects can be established based on the findings.

FIG. 5

Moving to Fig. 6, we see that wafers with high total defect counts do not translate to low wafer yield. With a UCL of 1400 defects, only one out of three wafers corresponds to below average yield. There is no correlation between total defects to yield. Therefore, one will be headed in the wrong direction if SPC is set based on total defect counts.

FIG. 6

On the other hand, Fig. 7 shows that high yield-impacting defects translate to low wafer yield. In this example, with a UCL of 1000 defects, all wafers that failed this control limit have below average yield. Therefore, SPC control can be established.

FIG. 7

As one can see, in-line monitoring is critical to the LED manufacturing process, and a method of separating yield-impacting defects from nuisance defects is needed. Given that the kill ratio correlates with defect attributes such as defect size, kill ratio analysis provides important guidance in setting defect attribute binning to identify yield-impacting defects. Moreover, the defect-to-yield correlation methodology provided in this article can help LED manufacturers learn more about yield-relevant defects systematically. LED manufacturers can then implement SPC to avoid expensive excursions and to realize optimum ROI.