Perhaps the primary theme at Strategies in Light (SIL) relating to the LED technology roadmap was whether the chip-scale package (CSP) will become predominant in terms of discrete LED packaging options. CSP implies an architecture in which there is virtually no package beyond the electrical p and n contacts that are metallized in the back-end manufacturing process. CSP technology has been widely used in the general semiconductor industry.
As the feature article on the keynotes describes, Jy Bhardwaj, senior vice president of research and development at Lumileds, predicted that chip-scale package technology can enable excellent LED performance and allow high-power LEDs to scale down to applications that are using mid-power LEDs, or up to high-output applications.
In the Advanced Technology Track, the debate over CSP was the theme of Thursday morning's session. Eun-Hyun Park, CEO of SemiconLight (part of Lumens Co), said his company is producing mid-power-class LEDs using chip-scale package technology. He said the technology enables low thermal resistance and uniform current spreading for low droop. He said the company built a chip-on-board assembly using 24 CSP LEDs, whereas 60 lateral die were required for the same lumen output, and the lateral die are 36% larger.
Mohiuddin Mala, director of research and product development at Lumileds, also spoke with a favorable view of CSP technology. He presented case studies of retrofit lamps and ceiling troffers, comparing traditional mid-power LEDs with CSP LEDs. Chip-scale package implementations have a lower bill of materials, said Mala, and smaller LED die area - so a more efficient utilization of the epitaxial manufacturing process.
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The contrarian view came courtesy of Paul Scheidt, LED product marketing leader at Cree. Scheidt discussed both wafer-level packaging (WLP) technology and CSP architectures. Scheidt argued that despite the potential to achieve savings by eliminating steps typically performed by a packaging house, some of those packaging steps are simply shifted to the die manufacturer.
Scheidt discussed the disadvantages of WLP and CSP. They ranged from the fact that you process bad die at the wafer level to optical light extraction issues with CSP. Scheidt said CSPs can raise cost on level-2 boards through the needs for highly-reflective substrates and higher-precision assembly. He concluded that WLP isn't commercially viable in the near term and CSP is finding little commercial success.
During the Q&A period after Scheidt's talk, he was challenged by Lumileds' Mala. Scheidt had referenced the claim Bhardwaj had made in the keynote that Lumileds had shipped a quarter-billion CSP LEDs in 2014. But Scheidt noted that Lumileds level-2 boards still use mid-power LEDs.
Mala said, "Lumileds has not officially launched CSP on the market." Scheidt replied, "Either you shipped them and they are launched or they are not." Mala implied that Lumileds has used the CSP LEDs internally at this point but did not specify in which products.
The debate will surely continue. We will dedicate a feature article on chip-scale package technology later this year. What's clear is that there is nothing simple about LEDs, the simplest active electronic component.
Maury Wright,
EDITOR
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